1. Field of the Invention
The present invention relates to a semiconductor memory device such as a NAND-type flash memory, more particularly to a semiconductor memory device having an on-chip error correcting function.
2. Description of the Related Art
The NAND-type flash memory is known to deteriorate its cell property through repeated operations of rewriting, and to vary data after it is left for a long time. In order to improve the reliability of the NAND-type flash memory, such a semiconductor memory that contains an ECC (Error Correcting Code) circuit mounted on-chip for error detection and correction has been proposed in the art (for example, Japanese Patent Application Laid-Open Nos. 2000-348497 and 2001-14888).
FIG. 21 is a block diagram briefly showing an arrangement of the conventional NAND-type flash memory with ECC circuits mounted thereon.
This memory comprises eight memory cell areas 10, 11, . . . , 17. Each of the memory cell areas 10, 11, . . . , 17 includes a plurality of memory cells, not depicted, arrayed in a matrix. Data of 528 bits (=one page) can be written in and read out from 528 memory cells connected to a common word line through 528 bit lines at a time. Page buffers 20-27 are connected to the memory cell areas 10-17, respectively. Each page buffer can hold 528-bit write data and read data. Between the page buffers 20-27 and I/O terminals 40-47 located corresponding to the memory cell areas 10-17, ECC circuits 30-37 are provided for the memory cell areas 10-17, respectively.
Each ECC circuit 30-37 has a coding function to add a certain bit number of check bits (ECC) to one page of information bits (528 bits) to be stored in each memory cell area 10-17, and a decoding function to detect and correct a certain bit number of errors in the information bits with the check bits added thereto. BCH (Bose-Chaudhuri-Hocquenghem) code is employed as an error correcting code that can correct a plurality of bit errors with a relatively small circuit scale. Between the memory and external, data is read and written on a basis of 8 bits corresponding to the number of memory cells. Data is fed bit by bit into each ECC circuit 30-37, and is circulated through and output from an internal cyclic shift register bit by bit to execute coding and decoding.
Operations of coding and decoding in the conventional ECC circuit 30-37 using BCH code will be described next.
The number of check bits in BCH code for correcting 2-bit errors and detecting 3-bit errors is equal to 21 bits for 528 information bits. For convenience of description, a simple error detection and correction system is described, which employs BCH code capable of correcting 2-bit errors and detecting 3-bit errors for the number of information bits, k=7, a code length, n=15, and the number of check bits, t=2.
In this case, a generating polynomial required for coding and decoding is given below as it is generally known:
                                                                        Fundamental                ⁢                                                                  ⁢                Polynomial                ⁢                                                                  ⁢                                  :                                ⁢                                                                  ⁢                                  F                  ⁡                                      (                    X                    )                                                              =                                                X                  4                                +                X                +                1                                      ⁢                                                  ⁢                                          α                ⁢                                                                  ⁢                Minimal                ⁢                                                                  ⁢                Polynomial                ⁢                                                                  ⁢                                  :                                ⁢                                                                  ⁢                                                      M                    1                                    ⁡                                      (                    x                    )                                                              =                                                X                  4                                +                X                +                1                                      ⁢                                                  ⁢                          α              3                        ⁢                                                  ⁢            Minimal            ⁢                                                  ⁢                          Polynomial              :                                                          ⁢                                                M                  3                                ⁡                                  (                  x                  )                                                              =                                    X              4                        +                          X              3                        +                          X              2                        +            X            +            1                          ⁢                                  ⁢                                                                              Generating                  ⁢                                                                          ⁢                  Polynomial                  ⁢                                                                          ⁢                                      :                                    ⁢                                                                          ⁢                  G                  ⁢                                                                          ⁢                                      (                    x                    )                                                  ⁢                                                                  =                                                      M                    1                                    ⁢                                      M                    3                                                                                                                          =                                                      X                    8                                    +                                      X                    7                                    +                                      X                    6                                    +                                      X                    4                                    +                  1                                                                                        (        1        )            (1) Coder
FIG. 22 is a block diagram showing a coder 10 functionally configured inside the conventional ECC circuit 3i (i=0, 1, . . . , or 7). The coder 10 comprises a shift register 11 consisting of registers D7, D6, D5, D4, D3, D2, D1, D0, XOR circuits 121, 122, 123, 124 for modulo-2 operations, and circuit changing switches SW1, SW2.
An operation for moving the shift register 11 once corresponds to multiplying each value in the shift register 11 by X. A value of data stored in the shift register 11 can be expressed by:a0X0+a1X1+a2X2+a3X3+a4X4+a5X5+a6X6+a7X7  (2)where ai denotes a value stored in a register Di, and ai=0 or 1 (i=0-7). When this is shifted once, the following is obtained:a0X1+a1X2+a2X3+a3X4+a4X5+a5X6+a6X7+a7X8  (3)From the generating polynomial G(x) given by Expression (1), a relation of X8=X7+X6+X4+1 is derived. Therefore, Expression (3) can be represented by:a7X0+a0X1+a1X2+a2X3+(a3+a7)X4+a4X5+(a5+a7)X6+(a6+a7)X7  (4)This corresponds to shifting each bit; storing the value a7 of the register D7 into the register D0; adding the values a3, a7 of the registers D3, D7 at the XOR circuit 121 and storing the sum into the register D4; adding the values a5+a7 of the registers D5, D7 at the XOR circuit 122 and storing the sum into the register D6; and adding the values a6+a7 of the registers D6, D7 at the XOR circuit 123 and storing the sum into the register D7.
On coding, the switches SW1, SW2 are first connected to ON sides to enter input data (information bits) I0, I1, I2, I3, I4, I5, I6 (I0-I6=0 or 1) bit by bit from external through the I/O terminal 4i. Every time one bit of the input data I0-I6 enters, the shift register 11 operates once. As the switch SW1 is kept ON during the input data I0-I6 entering, the data is output bit by bit to the page buffer 2i as it is. At the same time, the input data I0-I6 is added to the value a7 of the register D7 at the XOR circuit 121 and the sum is stored in turn into the shift register 11. After completion of the input data I0-I6 entered into the page buffer 2i, check bits I7, I8, I9, I10, I11, I12, I13, I14 are stored inside the registers D7, D6, D5, D4, D3, D2, D1, D0 of the shift register 11, respectively. The switches SW1, SW2 are then connected to OFF sides and, every time the shift register 11 operates, the check bits I7-I14 are output serially to the page buffer 2i through the switch SW1. The information bits and check bits stored in the page buffer 2i are written into the memory cell area 1i. At the same time, the value in the shift register 11 is reset.
(2) Decoder
A decoder is described next. The decoder comprises syndrome computational circuits and an error position detector. In the case of 2-bit error detection, two syndromes S1, S3 are required for decoding. These syndromes can be derived from the minimal polynomial M1(x)=X4+X+1 as it is known. FIG. 23 specifically shows (A) a conventional S1 syndrome computational circuit 20 and (B) a conventional S3 syndrome computational circuit 30.
Based on the minimal polynomial M1(x), the S1 syndrome computational circuit 20 in FIG. 23A comprises a shift register 21 consisting of registers D3, D2, D1, D0, and XOR circuits 221, 222. An operation for moving the shift register 21 once corresponds to multiplying a value in the shift register 21 by X. The value stored in the shift register 21 can be expressed by:a0X0+a1X1+a2X2+a3X3  (5)where ai denotes a value stored in a register Di, and ai=0 or 1 (i=0-3). When this is shifted once, the following is obtained:a0X1+a1X2+a2X3+a3X4  (6)From the α minimal polynomial M1(x), a relation of X4=X+1 is derived. Accordingly:a3X0+(a0+a3)X1+a1X2+a2X3  (7)This corresponds to shifting each bit; storing the value a3 of the register D3 into the register D0; and adding the values a0, a3 of the registers D0, D3 at the XOR circuit 122 and storing the sum into the register D1. The information bits I0-I6 and check bits I7-I14 are fed in this order into the S1 syndrome computational circuit 20 bit by bit. The shift register 21 operates once every time one bit enters. After all bits I0-I14 enter, the syndrome S1 is generated in the shift register 21 (D0-D3).
Similar to the S1 syndrome computational circuit 20, the S3 syndrome computational circuit 30 in FIG. 23B comprises a shift register 31 consisting of registers D3, D2, D1, D0, and XOR circuits 321, 322, 323, 324. It is configured by the X3 circuit of the minimal polynomial M1(x). In the S3 syndrome computational circuit 30, an operation for moving the shift register 31 once corresponds to multiplying a value in the shift register 31 by X3. The value stored in the shift register 31 is expressed by Expression (5). When it is multiplied by X3, the following is given:a0X3+a1X4+a2X5+a3X6  (8)From the α minimal polynomial M1(x), a relation of X4=X+1 is derived. Accordingly:a1X0+(a1+a2)X1+(a2+a3)X2+(a0+a3)X3  (9)This corresponds to shifting each bit; storing the value a1 of the register D1 into the register D0; adding the values a1, a2 of the registers D1, D2 at the XOR circuit 322 and storing the sum into the register D1; adding the values a2, a3 of the registers D2, D3 at the XOR circuit 323 and storing the sum into the register D2; and adding the values a0, a3 of the registers D0, D3 at the XOR circuit 324 and storing the sum into the register D3. The information bits I0-I6 and check bits I7-I14 stored in the memory cells are also fed in this order into the S3 syndrome computational circuit 30 bit by bit. The shift register 31 operates once every time one bit enters. After all bits I0-I14 enter, the syndrome S3 is generated in the shift register 31 (D0-D3).
FIG. 24 is a flowchart showing an algorithm for decoding. The S1, S3 syndrome computational circuits 20, 30 compute syndromes S1, S3 first based on the information bits and check bits read out from the memory cell area 1i (step S1). If the syndromes S1, S3 are S1=S3=0, it is determined errorless, and the read-out information bits are output as they are (steps S2, S3, S4). If only one of the syndromes S1, S3 is equal to 0, it is determined uncorrectable, and the data is output as it is (steps S2, S3, S5, S6, S7). If S1≠0 and S3≠0, computations are executed to derive σ1=S12 and σ2=S13+S3 (steps S2, S6, S8). If σ2=0 (step S9), it can be found that a 1-bit error is present, and 1-bit corrected data is output (step S10). If σ2≠0 (step S9), it can be found that 2-bit errors are present, and 2-bit corrected data is output (step S11).
The position of the error bit can be found by assigning Z=αI (I=0, 1, 2, 3, 4, 5, 6) in turn to an error position polynomial σ(Z) represented by Expression (10) as it is known generally. The position of the error can be indicated by i that holds σ(αI)=0.σ(Z)=S1+σ1×Z+σ2×Z2  (10)
An arrangement of the error position detector is shown in FIGS. 25 and 26, which is configured based on such the point. FIG. 25 shows a first arithmetic section 40a that computes and stores S1, σ and σ2. FIG. 26 shows a second arithmetic section 40b that executes the operation of Expression (10) based on the operated result from the first arithmetic section 40a and outputs a detection signal to indicate the error position in the data. As shown in FIG. 25, the first arithmetic section 40a comprises a shift register 41, an X arithmetic circuit 42, and an X2 arithmetic circuit 43. A shift register 41a stores the syndrome S1, and shift registers 42a and 43a store the operated results, σ1=S12 and σ2=S13+S3. It is assumed that the shift register 42a has a value of:a0X0+a1X1+a2X2+a3X3  (11)where ai denotes a value stored in a register Di, and ai=0 or 1 (i=0-3). As the X arithmetic circuit 42 multiplies it by X, the value of the shift register 42a comes to:a0X1+a1X2+a2X3+a3X4  (12)From the α minimal polynomial M1(x), a relation of X4=X+1 is present. Accordingly, Expression (12) yields:a3X0+(a0+a3)X1+a1X2+a2X3  (13)This corresponds to shifting each bit; storing the value a3 of the register D3 into the register D0; and adding the values a0, a3 of the registers D0, D3 at the XOR circuit 422 and storing the sum into the register D1.
The X2 arithmetic circuit 43 multiplies the value of the shift register 43a by X2. Therefore, when the value indicated by Expression (11) is stored in the shift register 43a, and it is multiplied by X2, the value of the shift register 43a comes to:a0X2+a1X3+a2X4+a3X5  (14)From the α minimal polynomial M1(x), a relation of X4=X+1 is present. Accordingly, Expression (14) yields:a2X0+(a2+a3)X1+(a0+a3)X2+a1X3  (15)This corresponds to shifting each bit; storing the value a2 of the register E2 into the register E0; storing the value a1 of the register E1 into the register E3; adding the values a2, a3 of the registers E2, E3 at the XOR circuit 43b1 and storing the sum into the register E1; and adding the values a0, a3 of the registers E0, E3 at the XOR circuit 43b2 and storing the sum into the register E2.
When 1-bit data I0-I6 is output, one shift operation of the shift registers 41a, 42a, 43a multiplies the term of σ1 by Z in the X arithmetic section 42 and the term of σ2 by Z2 in the X2 arithmetic section 43. The NAND-type flash memory operates the shift registers 41a, 42a, 43a in synchronization with the toggle signal that is employed to output the information bits stored in the memory cell to outside the chip. In the second arithmetic circuit 40b, the result from the operation through an XOR circuit 44 and an NOR gate 45 exhibits ‘1’ at the error position. This output is employed to invert the corresponding data Ii to detect and correct the error.
Thus, in the conventional ECC circuit that employs BCH code, one shift and computation per 1-bit input is the basic operation. The NAND-type flash memory receives parallel data input from external on a basis of 8-I/O or 16-I/O per address. Therefore, it is required to correct an error per I/O or compute 8 or 16 times during the one input. The 8 or 16-time computation during the one input needs a fast operation for this part, which can not be achieved practically because a special process is required, for example.
Therefore, an ECC circuit 3i is provided for each memory cell area 1i (each I/O) in the art to correct errors on a basis of each memory cell area 1i. The NAND-type flash memory reads and programs data per page (528 bytes). If it intends to correct 2-bit errors and detect 3-bit errors per I/O, it requires 21 check bits for 528 information bits, 21×8=168 extra check bits in total for the entire chip. This is an inhibit factor for improving the chip integration density.
The present invention has been made in consideration of such the problem and accordingly has an object to provide a semiconductor memory device capable of reducing the number of check bits relative to the number of information bits to improve a chip integration density.